This invention relates to an analog to digital converter comprising a sigma-delta modulator followed by a decimating digital filter. This analog to digital converter is e.g. known from the article: "The Application of Delta Modulation to Analog to PCM Encoding" By D. J. Goodman, published in "The Bell System Technical Journal", Volume 48, nr Feb. 2, 1969.
The continuing decrease of the component size of modern CMOS-integrated circuits necessitates a reduction in the circuit supply voltage for reasons of maintaining a high standard of reliability. The supply voltage may conveniently be reduced to values as low as 3 Volts or lower. However such a low supply voltage is a nuisance for A/D (analog to digital) conversion schemes based on sample, hold and amplitude quantization, because of the entailed reduction in the resolution available within the amplitude range. On the other hand, the decrease of the component size has a beneficial effect on the obtainable time resolution in the circuitry, owing to the increase in the intrinsic speed of the transistors.
Therefore it is advantageous to use an A/D-conversion scheme where the information of the analog signal is turned from the amplitude axis to the time axis and when subsequently the time axis, rather than the amplitude axis, is quantized. This can conveniently be implemented by means of a synchronous sigma-delta modulator which is followed by a decimating digital filter, as is described in the above mentioned publication.
A synchronous sigma-delta modulator basically consists of a feedback loop comprising a clock-pulse switched comparator, whose binary output signal is combined with the analog input signal and wherein the combined signal is fed to the input of the comparator. Conventionally the combined signal is applied to the input of the comparator through an integrating analog filter, however it is also possible to use instead separate integrating analog filters for the analog input signal and for the binary output signal of the switched comparator prior to their combination.
The output signal of the comparator consists of a stream of synchronous binary (two-valued) samples (e.g. 0 and 1, or -1 and +1), whereby the number of samples of one value per unit of time is approximately proportional to the amplitude of the analog input signal. The bit-rate of the binary samples is determined by the rate of the clock-pulses which switch the comparator. The binary output signal of the synchronous sigma-delta modulator is subsequently applied to a decimating digital filter which transforms the binary signal to a bit-parallel digital signal at lower clock rate, so that a pulse code modulated (PCM) signal is obtained. The above mentioned publication proposes a digital transversal filter followed by a subsampling circuit for this function.
A drawback of the above described A/D-converter is that for broadband signals, such as video signals, the clock-frequency of the synchronous sigma-delta modulator has to be rather high, so that it is difficult to realize a reliable, simple and robust arrangement with present day integrating techniques. The difficulty is that in the case of such synchronous sigma-delta modulation a decision operation has to be carried out on a very weak input signal in a very small time at a high repetition rate. Practical decision switches, which consist of clocked bistable circuits, do not fulfil all these requirements because they are not able to sufficiently quickly restore from their previous decision operation. Consequently, the decisions made by the switch are unreliable, resulting in increased noise. The invention has for its object to provide a more reliable A/D-converter of the kind described in the preamble and the analog to digital converter according to the invention is characterized in that the sigma-delta modulator is an asynchronous sigma-delta modulator, generating an asynchronous duty cycle modulated square wave, and that between the output of the asynchronous sigma-delta modulator and the decimating digital filter clock-controlled sampling means are provided. Therefore, unlike in the case of synchronous sigma-delta modulation, the clock controlled sampler is now placed outside the loop of the sigma-delta modulator. In the proposed configuration, the decision is executed on large input signals, resulting in a much more robust operation.
An asynchronous sigma-delta-modulator consists of a feedback configuration with an integrating lowpass filter and a comparator, in which the output of the comparator, combined with the input signal, is fed to the input of the lowpass filter. The comparator is not switched by an externally applied clock pulse. The asynchronous sigma-delta modulator, if properly designed, generates an asynchronous square wave. The generated square wave has a duty cycle which is approximately linearly dependent on the input signal and an instantaneous frequency which is non-linearly dependent on the input signal.
Such asynchronous sigma-delta modulator, which is simple, does not require any clocking, matches well with mainstream CMOS-technology and can operate at low currents and supply voltage, is known per se e.g. from an article by C. J. Kikkert et al., "Asynchronous Delta Sigma Modulation". Proceedings of the IREE of Australia, Vol. 36, April 1975, pp. 83-88.
The second step in the AD-conversion process is the discretization of the time axis. This may be done by sampling the duty cycle modulated asynchronous square wave, generated by the asynchronous sigma-delta modulator, at a sufficiently high clock rate. This sampling results in a stream of two-valued synchronous samples which, if subjected to a holding operation over the entire sampling period, would result in a duty cycle modulated square wave with synchronous leading and trailing edges, which is approximately similar to the asynchronous square wave generated by the asynchronous sigma-delta modulator. The difference between the edge positions of the asynchronous square wave and the edge positions of the synchronized equivalent, may be considered as the quantization noise. This quantization noise is smaller the higher the clock rate is at which the sampler operates.
The binary output pulses of the sampler are subsequently processed by the decimating digital filter for obtaining a suitable digital format such as a PCM-signal. The decimating digital filter may comprise a digital transversal filter, as is described in the above mentioned article of D. J. Goodman. Another solution for the decimating digital filter may comprise a recursive bitstream converter, as described by the inventor in IEEE Transactions on Circuits and Systems, 40, nr. 2, pp 65-72 of February 1993. Such recursive bitstream converter is conceptually equivalent to a comb-filter, followed by a subsampler and a spectrum correction filter.